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Hello! I'm TR of R&D department.
In this article, I would like to talk about the technological development of copper plating solution that suppresses the coefficient of thermal expansion (CTE) of copper-plated wiring, which tends to cause problems in the heat treatment process due to the mismatch of the CTE between the substrate materials.
Copper plating with high risk of product quality due to mismatch of coefficient of thermal expansion
When designing and studying manufacturing processes for electronic device products, the effects of thermal expansion of the electronic materials used in the products are taken into consideration. This is because temperature changes in the manufacturing process and usage environment have a great impact on the characteristics and quality of products.
Many wires used in electronic devices are made of copper plating. The coefficient of thermal expansion (CTE) of copper is 17ppm / K, while the CTE of silicon is as small as 3ppm / K, and insulation materials made of resin, on the other hand, generally exhibit a higher CTE than the metals used in wiring materials. Therefore, in the glass epoxy board used for printed circuit boards, thermal expansion is suppressed by mixing inorganic materials such as glass cloth or alumina, and polyimide film that have low CTE characteristics have also been developed.
On the other hand, efforts to control the CTE of copper-plated wiring have not progressed so far.
In the heat treatment process after forming the copper-plated wiring, problems such as cracks, disconnections, and peeling of the wiring, misalignment of the wiring occur at places where internal stress is concentrated due to thermal expansion and robot transferring problems also occur due to the warpage of the entire substrate. It is necessary to consider the design and process to avoid the occurrence of such defects, which is also a factor of cost increase.
In addition, it is necessary to ensure connection reliability that meets the required life even in the product usage environment, but in harsh usage environments, there would be the risk of quality defects may occur due to the mismatch of the CTE between the materials used for the product.
Alternatives of metallic materials with a smaller coefficient of thermal expansion than copper
If it is difficult to take measures against the risk due to thermal expansion with conventional copper-plated wiring, use a metal such as nickel, which has a smaller CTE than copper, or alloy with a metal such as tungsten or molybdenum. However, the disadvantages of high electrical resistance, low thermal conductivity, and high cost may lead to the inability to bring out the original product characteristics.
If copper wiring can be formed by conventional electroplating process, while controlling CTE without increasing electrical resistivity characteristics that shows second lowest next to silver, there will be a great advantage at low cost because it does not require major changes in the existing manufacturing process.
Practical application of low CTE copper plating solution - Efforts of Tosetz
In order to solve the problems so far, Professor Kazuo Kondo of Osaka Prefectural University (currently President of Fine Feature Electrodeposition Research Laboratory Co., Ltd.) has invented epoch-making low CTE copper wiring by adding special additives in copper plating solution.
Through subsidy project (supporting industry) adopted by the Ministry of Economy, Trade and Industry (METI) in 2017, we are cooperating in the development of plating equipment required for the practical application of low CTE copper plating solution of Fine Feature Electrodeposition Research Laboratory Co., Ltd.
The website of Fine Feature Electrodeposition Research Laboratory Co., Ltd. is here, so if you are interested in the technology, please come and see it!
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Future challenges
For electronic devices compatible with 5G communication standards and next-generation power semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO) that require high-temperature operation, severe operating temperature conditions are required than ever. CTE mismatch between silicon or compound substrate material and the electrode material is required to be as small as possible.
In addition, the fan-out wafer level package (FO-WLP), which is an advanced packaging method used in smartphones, a fan-out panel level package (FO-PLP) has been developed that applies the technology to large substrates. However, even in these applications, it is required to minimize the influence on the warpage of the substrate and the misalignment of the wiring caused by the CTE mismatch between the materials in the heat treatment process after forming the copper-plated wiring.
Lastly
What do you think?
The application of low thermal expansion copper plating may improve the manufacturing process yields and the long-term reliability of various electronic device products and packaging.
Tosetz, we are also working on the development of equipment that can realize such new technologies!
Click here if you are interested in Tosetz.
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